1. Field of the Invention
The present invention relates to a clocked inverter and also relates to a shift resister including a clocked inverter as a unit circuit. Further, the present invention relates to electric circuits such as a NAND and a NOR.
2. Description of the Related Arts
In recent years, display devices such as a liquid crystal display device and a light emitting device have been developing greatly because of the growth in demand of mobile machines. A technique for integrating a pixel and a driver circuit (hereinafter, internal circuit) using a transistor formed of a polysilicon semiconductor on an insulator has been developing greatly, because the technique can contribute to miniaturization of devices and less electric power consumption. The internal circuit formed on an insulator is connected with a controller IC or the like (hereinafter, external circuit) thorough a FPC or the like to be controlled.
Generally, the power source voltage of an internal circuit is approximately 10 V whereas an IC that constitutes an external circuit prepares a signal with approximately 3 V amplitude, since the IC can operate with lower power source voltage than an internal circuit. In order to accurately operate an internal circuit with the signal with approximately 3 V amplitude, there is a shift register in which a level shift portion is arranged in each stage. (Reference 1. Japanese Patent Laid-Open No. 2000-339985)
FIGS. 11A, 11B, 11C and 11D show a circuit diagram of a clocked inverter, a logic symbol of the clocked inverter, a circuit diagram of a NAND and a circuit diagram of a NOR, respectively.
When level shifting is performed in an internal circuit, problems are caused, for example, in increase in occupation area of a driver circuit, reduction of frequency property due to delayed or blunted waveforms. Furthermore, as described in the Reference 1, it is necessary to suppress fluctuation in TFT characteristics between adjacent TFTs when the current driving type of shift register is used. On the contrary, when a level shifter is arranged in an external circuit, problems are caused, for example, growth in total size of a casing for devices due to the increase in the number of components such as IC, in cost for manufacturing and in power consumption by the shift register. Accordingly, it is preferable to use a signal with approximately 3 V amplitude without level shifting.
Further, a threshold voltage of a TFT is fluctuated because of fluctuation in film thickness of a gate insulating film or in gate length and gate width caused by differences of used substrates or manufacturing steps, and thus the threshold voltage value may be different from an expected value. In such case, when a signal with a small amplitude, approximately 3 V amplitude is used in a digital circuit in which two logical level, 1 and 0 are used, the TFT may not be operated accurately due to the influence of the fluctuation in the threshold voltage.